1. Field of the Invention
The present invention relates to an I/O subsystem and the exclusive control method, data storage method and memory initialization method in the I/O subsystem.
2. Description of the Related Art
A recent large computer system which has increasingly enlarged the scale is generally composed of a plurality of central processing units (CPUs). In such a system, common use of data and communication of data among a plurality of CPUs are necessary. For this purpose, I/O device subsystem including an external storage unit is required to be provided with a multiplicity of host interfaces.
To meet this demand, the I/O subsystem is provided with a multiplicity of input/output controllers (CAs: Channel Adapters) having a plurality of input/output interfaces which are connected to host CPUs. In order to exclusively control the accesses from a plurality of CPUs, the I/O subsystem is provided with an exclusive control manager (RM: Resource Manager) having an exclusive control table.
FIG. 1 shows the structure of a semiconductor disk apparatus as such an I/O subsystem. In FIG. 1, the reference numerals 1a, 1b each represent a CPU, 2 a semiconductor disk controller, and 3 a semiconductor disk having a plurality of semiconductor memory modules 3a, 3b, 3c, . . . The semiconductor disk apparatus has the same structure (command code, data transfer method, etc.) as that of a magnetic disk apparatus except that the magnetic disk as the recording medium is replaced by a semiconductor memory. Therefore, the interface between the CPU 1a (1b) and the semiconductor disk controller 2 is completely the same as the interface between the CPU 1a(1b) and a magnetic disk controller. This semiconductor disk apparatus is advantageous in that instant access is possible because the movement of the head, which is necessary in a magnetic disk, is not necessary, and in that the software resources between the CPU and the magnetic disk controller are usable as they are.
In the semiconductor disk controller 2, the reference numerals 2a and 2b each represent a channel adapter CA having a single or a plurality of interfaces (host interfaces) to and from a host apparatus (CPU), numerals 2c and 2d each a memory interface adapter for controlling the operation of writing/reading data into and from the semiconductor disk 3, numeral 2e represents a resource manager RM having an exclusive control table ECT and-executing exclusive control for permitting a host interface to use the semiconductor module 3a (3b or 3c) when another host interface is not using it, while prohibiting the use when another host interface is using it. Exclusive control is executed in each semiconductor memory module.
Two physical interfaces (physical ports) 2a0, 2a1 (2b0, 2b1) are provided between the channel adapter 2a (2b) and the CPU 1a (1b). The exclusive control table ECT of the resource manager 2e records whether or not each of the semiconductor memory modules 3a, 3b, 3c (device numbers 0 to 2) is occupied by each combination (path) of a channel adapter (channel number) and a physical interface mounted on each channel adapter, as shown in FIG. 2. There are four types of paths, i.e., (00), (01), (10) and (11) in the semiconductor disc controller 2.
In this I/O subsystem, if a command for access to the semiconductor memory module 3b is issued from the CPU 1b to the channel adapter 2b through the physical interface 2b1, for example, the channel adapter 2b requests the resource manager 2e to permit the use of the semiconductor module 3b. When the resource manager 2e receives the request for use, it judges whether or not the semiconductor memory module 3b is being used through another path by reference to the exclusive control table ECT. If the answer is YES, the resource manager 2e does not permit the channel adapter 2b to use it. On the other hand, if the answer is NO, the resource manager 2e permits the channel adapter 2b to use it, and sets a flag indicating xe2x80x9cOccupiedxe2x80x9d in the field of the semiconductor memory module 3b in correspondence with the path (11). The channel adapter 2b which is permitted to use the semiconductor memory module 3b then receives data from the CPU 1b through the physical interface 2b1, and writes the data into the semiconductor memory module 3b through the memory interface adapter 2d. When the writing operation is finished, the resource manager 2e changes the flag indicating xe2x80x9cOccupiedxe2x80x9d to a flag indicating xe2x80x9cVacantxe2x80x9d in correspondence with the path (11).
Problem in Exclusive Control
As described above, in the conventional I/O subsystem, a table region on the exclusive control table ECT is pre-allotted for each of the channel adapters in the I/O subsystem. For this reason, if the number of channel adapters accommodated in the I/O subsystem is increased and the number of physical interfaces in each channel adapter is increased, the size of the exclusive control is enlarged.
With the recent development and change of data transmitting technique, many kinds of interface systems (e.g., electric interface system, optical interface system and OC link) coexist. In this situation, in order to enable an I/O subsystem to be connected to as many CPUs as possible, it is necessary to correspond to all of the existing interface systems. In other words, it is necessary to provide various types of channel adapters in the I/O subsystem in order to correspond to every interface system and, as a result, the number of channel adapters therefore increases. In addition, since not only the physical data transfer means but also the number of physical interfaces which can be provided in one channel adapter are different in interface systems. Therefore, the exclusive control table is further enlarged.
If a plurality of logical interfaces are defined on one physical interface, the exclusive control table must be produced while taking each logical interface into consideration. FIG. 3 is an explanatory view of an OC link interface system. In FIG. 3, the reference numeral 4a represents a channel adapter for OC link, and 4b an OC link change-over/repeater provided between a CPU 4ci (i=1, 2, . . . ) and the I/O subsystem so as to dynamically switch the interface. It is possible to define 256 CPUs at its maximum on one physical interface through the OC link change-over/repeater. When a plurality of logical interfaces are defined on one physical interface in this way, it is necessary to produce the exclusive control table ECT while dealing with each of the logical interfaces as if they were different physical interfaces.
There is a system called a multi-exposure system which enables a multiple access by defining a plurality of I/O device addresses with respect to one I/O device. The multi-exposure system is used as an I/O device access system which is able to simultaneously access a plurality of areas in the I/O device such as a magnetic drum apparatus, a semiconductor disk apparatus and a disk cache through different paths. A computer has an architecture called virtual machines (separate operating systems which are operated independently of each other on a single CPU). When a plurality of such virtual machines (operating systems) are operated, one exposure is allotted to one operating system so as to secure the independence of the I/O device access of each operating system. In this way, when there are a plurality of virtual machines, a plurality of logical interfaces exist on one physical interface. In this case, it is also necessary to produce the exclusive control table ECT while dealing with each of the logical interfaces as if they were different physical interfaces.
FIG. 4 is an explanatory view of a multi-exposure system. It is now assumed that 256 I/O device addresses such as (00)hex to (FF)hex can be defined on an interface. At this time, the zone bits of an address is assigned to an exposure number. For example, as shown in FIG. 4A, the first 2 bits are assigned to an exposure number and the last 6 bits are assigned to a device number. In other words, exposures 0, 1, 2 and 3 are defined. If it is assumed that the number of physical I/O device in the I/O subsystem is one, and the device number is 0, the relationship shown in FIG. 4B holds between an exposure number and an I/O device address. These four I/O device addresses designate the same physical device (duplicate definition). The number of exposures may be other than four and the bit positions indicating the exposure number may be different.
As described above, in the conventional I/O subsystem, a table region is stationarily allotted on the exclusive control table in accordance with the maximum possible structure of the I/O subsystem. In this system, it is necessary to secure a large table area on the exclusive control table, so that a large storage region is required. FIG. 5 shows an example of the structure of a conventional exclusive control table. In this table, the symbol n1 represents the maximum number of channel adapters mounted in the I/O subsystem, n2 the maximum number of physical interfaces mounted on one channel adapter, and n3 the maximum number of logical interfaces defined on one physical interface. The number of items in the column is n1xc3x97n2xc3x97n3. In the actual subsystem, however, the number of physical interfaces on one channel adapter and the number of logical interfaces on one physical interface vary, and a large part of the table is generally vacant, so that it is wasteful to produce a large exclusive control table.
Problem in Semiconductor Memory
In the semiconductor disk apparatus, a semiconductor memory chip is used as a medium for storing data. For this reason, the memory cost per bit is more expensive than that in a magnetic disk apparatus. In addition, the storage capacity per semiconductor disk apparatus is smaller as compared with a magnetic disk apparatus. In order to solve the problem in the storage capacity, the shape of a semiconductor memory chip is devised or the method of mounting the semiconductor memory chip is improved, but both of these improvements have a limitation, and the problem of the cost still remains unsolved. In order to solve the problem of the cost, a technique of storing as large an amount of data as possible in the physically same semiconductor memory resource is necessary.
In a conventional semiconductor disk apparatus, a format (CKD format) similar to that in an actual magnetic disk apparatus is adopted at the time of emulation. That is, an area on the semiconductor memory is allotted to gap information, which is necessary for controlling the operation of inputting/outputting data to and from a magnetic disk medium.
FIG. 6 shows a data format in a conventional semiconductor disk apparatus. The symbol DIR represents a directory written at the head of a track field. This data is intrinsic to a semiconductor disk and does not exist in the actual magnetic disk apparatus. After the directory DIR, a plurality of records Ri each of which is composed of a count portion Ci (i=1, 2, . . . ), a key portion Ki and a data portion Di are written. The count portion Ci records a track address, a record number, and the lengths of the subsequent key portion Ki and data portion Di. The key portion Ki is not always necessary but records a key for retrieval by an access method. The data portion Di records data which are generally called xe2x80x9cuser dataxe2x80x9d. Each adjacent recording portions are divided by a gap g.
Such a gap g is unnecessary for accessing the semiconductor memory. Therefore, by removing all the gaps g, a larger amount of data is stored in the same physical semiconductor memory resource. However, since these gap areas are very small as seen from the total region of the subsystem, removal of the gap areas cannot be said to be a very effective solution.
As a technique which is worth notice, a data compressionxe2x80xa2restoration technique has recently been developed. This is a technique of compressing data so as to reduce the original data size without impairing the contents of the data, storing the compressed data in an external storage medium, and restoring the compressed data to the original data when the data is actually processed. There are various methods for this technique. The typical method is a method of encoding data in accordance with the continuity of the data in a block of data strings, and includes a run-length encoding method and a universal encoding method. In the run-length encoding method, data xe2x80x9caxe2x80x9d, for example, is compressed by representing xe2x80x9caaxe2x80x9d by xe2x80x9ca2xe2x80x9d and xe2x80x9caaaaaxe2x80x9d by xe2x80x9ca5xe2x80x9d.
In the universal encoding method, input data are encoded by using the information representing a partial data string which has already been encoded. The typical universal encoding method adopts a Ziv-Lempel code. (See, for example, Munakata, xe2x80x9cData Compression Method by Ziv-Lempelxe2x80x9d Information Processing Vol. 26, No. 1, 1985.) In the Ziv-Lempel encoding method, two algorithms, (1) a universal type and (2) an incremental parsing type, are proposed. As a practical method using a universal type algorithm, there is an LZSS encoding method (T. C. Bell, xe2x80x9cBetter OMP/L Text Compressionxe2x80x9d, IEEE trans. on Commun, Vol. COM-34, No.12, December 1986). As a practical method using an incremental parsing type algorithm, there is an LZW (Lempel-Ziv-Welch) encoding method (T. A. Welsh, xe2x80x9cA Technique for High-Performance Data Compressionxe2x80x9d, Computer, June 1984.)
In the case of writing a large amount of data in the physically same semiconductor memory, adoption of a method of writing compressed data and restoring it to the original data when reading is considered. However, there are some problems remaining unsolved in the data compression technique.
A first problem is that a long time is required for data compression, i.e., the overhead time which is necessary for data transfer. Although there is a slight variation according to the methods of data compression, data compression processing fundamentally necessitates processing such as buffering of the data for monitoring the pattern of the data and the registration and retrieval of encoded data. For this reason, the data transfer time for compressed data is longer than that for data which is not subjected to any processing. Such an overhead time cannot be disregarded in a semiconductor disk apparatus which enables a uniform and high-speed access irrespective of the type of data.
A second problem is that the size of compressed data cannot be estimated before actual compression. As a result, in the case of reading stored data and rewriting it after modifying a part thereof, it is not always possible to store the data at the same position because the size of the compressed data is different from the compressed data before modification. If the run-length encoding method is cited as an example, when data xe2x80x9caaaaxe2x80x9d encoded as xe2x80x9ca4xe2x80x9d and stored in the semiconductor memory is modified to xe2x80x9caabaaxe2x80x9d, the compressed data becomes xe2x80x9ca2ba2xe2x80x9d, so that the size of the compressed data increase. In addition, since the data compression ratio depends on the type of data, if data are not continuous or the pattern of the data or the frequency of data occurrence is not constant, compression is generally impossible. In the worst case, the size of compressed data becomes larger than that of the original data.
A third problem is that since the original data is compressed, when there is an abnormality in a data compression mechanism or the like, the abnormality cannot be found until the compressed data is restored to the original data.
It is necessary to solve these problems in order to increase the amount of data which is stored in the semiconductor memory by adopting the data compression restoration method.
Problem in Memory Initializing Time
In a storage unit using a volatile memory such as a semiconductor disk apparatus, when the power source is initially turned on or when a print board with memory module is mounted or removed, the contents of the memory become undefined. In this case, the initializing operation for writing specific data (initialization data) in the memory so as to initialize the memory is necessary. Since the apparatus cannot be used until the initializing operation is finished, the user must wait for a while after the power source is turned on. In addition, since the access controller executes the initializing operation, memory access is impossible during initialization. It is therefore necessary to reduce such inconveniences in a storage unit as much as possible by shortening the initialization time or improving the memory access path.
FIG. 7 shows a conventional initializing mechanism. When the power source is turned on, an initialization starting signal INS is produced in a host module or an access controller 11. A data register 12 receives the initialization starting signal INS and sets writing data IDT for initialization therein. An initialization address counter 13 outputs an initialization address IAD. An address switching circuit 14 changes an address signal AD from the host module over to the initialization address IAD, and outputs the initialization data IDT to a data bus 15, the initialization address signal IAD to an address bus 16, and a memory access timing signal (not shown) so as to execute the operation of initializing a storage unit 10. Herein, REF denotes a refresh command signal and IED denotes an initialization end signal.
FIG. 8 shows the structure of another conventional initializing mechanism. In this mechanism, two access controllers 11a, 11b access three memory portions 10a, 10b and 10c separately from each other. Each of the access controllers 11a, 11b has the same structure as the access controller 11 shown in FIG. 7. When the memory portion 10b at the center is added by mounting a print board for memory module, the upper access controller 11a accesses the memory portion 10b so as to initialize it in the same way as in the mechanism shown in FIG. 7. During the initialization of the storage portion 10b, the lower access controller 11b receives an address signal AD and a data signal DT from the host module and outputs these signals to the address bus 16 and the data bus 15, respectively, and further outputs a storage access timing signal (not shown) so as to access the other two storage portions 10a and 10c in response to the request for access from the host module.
As described above, initialization is conventionally executed by producing an initialization address and writing initialization data into a memory in accordance with the address by an access controller. In the case of initializing a volatile memory, a refreshing operation for holding the data in the memory is necessary. Therefore, when a refresh command signal REF (see FIG. 7) is input, the initialization address counter 13 suspends the production of an initialization address signal IAD, and after the refreshing operation is finished, it resumes the production of an initialization address signal IAD. As a result, the time required for initialization is the sum of the time for writing the initialization data IDT and the time for executing the refreshing operation.
If initialization takes a long time, since the request for access from the host module cannot be processed until the end of the initialization, the user who has turned on the power source must wait for a long time before he can actually use the apparatus. In the mechanism shown in FIG. 8, the other access controller can process the request for access from the host module, but the memory access performance of the apparatus as a whole is reduced to half during that time. That is, if initialization takes a long time, the performance is also greatly lowered even in this mechanism.
As described above, in a conventional I/O subsystem, the exclusive control table is large and a large memory for storing the exclusive control table is required.
Furthermore, the operation of writing compressed data into a conventional semiconductor disk apparatus suffers from various problems such as (1) that the increase in the transfer time cannot be disregarded, (2) that it is impossible to estimate the size of compressed data in advance and (3) that when an abnormality is caused in the compression control mechanism, it is impossible to find the abnormality until the data is restored.
In addition, since a refreshing operation is necessary for initializing a semiconductor memory or the like, the waiting time for access is long.
Accordingly, it is a first object of the present invention to eliminate the above-described problems in the related art and to provide an I/O subsystem having an enhanced performance.
It is a second object of the present invention to provide an exclusive control method and an I/O subsystem which can reduce the size of an exclusive control table.
It is a third object of the present invention to provide a data storage method and an I/O subsystem for storing compressed data in a semiconductor disk apparatus which can solve the problems in data compression in the related art.
It is a fourth object of the present invention to provide an initialization method and an I/O subsystem which can shorten the time for initializing a semiconductor memory or the like by obviating a refreshing operation.
To achieve the first and second objects, in a first aspect of the present invention, there is provided an exclusive control method comprising the steps of: allotting a logical path number to each of the host interfaces in each of the input/output interface portions; managing the state of ue of I/O devices in correspondence with the logical path number in an exclusive control table; judging whether or not an I/O device is being used by another host interface by reference to the exclusive control table when a request for use of the I/O device is input from a host interface to which a predetermined logical path number is allotted; permitting the host interface which has required for access to use the I/O device when the I/O device is not in use, while setting a flag indicating that the I/O device is xe2x80x9cOccupiedxe2x80x9d in the exclusive control table in correspondence with the allotted logical path number; and changing the flag to a flag indicating that the I/O device is xe2x80x9cVacantxe2x80x9d when the use of the I/O device is finished. There is also provided an I/O subsystem which realizes this exclusive control method.
To achieve the third object, in a second aspect of the present invention, there is provided a data storage method for storing data in a semiconductor memory module, the method comprising the steps of: compressing the data by a channel adapter and writing the compressed data in the semiconductor memory module, reading and restoring the compressed data from the semiconductor memory module; and verifying the compressed data written in the semiconductor memory module by comparing the restored data with the data before compression. There is also provided an I/O subsystem which realizes this data storage method.
To achieve the fourth object, in a third aspect of the present invention, there is provided a memory initialization method for initializing a volatile memory which is accessed in accordance with combination of a designated column address and a designated row address and which is refreshed for each row by writing initialization data into the memory, the method comprising the steps of: writing the initialization data in all memory cells on an i-th column while consecutively producing row addresses in an ascending order with the column address fixed at a constant value i; and repeating the step of writing the initialization data in the same way on subsequent columns while serially advancing the column address one by one.
Other features and advantages of the present invention will be apparent from the following description taken in conjunction with the accompanying drawings.